The present invention pertains generally to capacitor placement in electronic circuits, and more particularly, to a via-sharing technique that increases the capacitor density and decreases the number of vias required for capacitor placement on a printed circuit board.
Digital circuits consume high instantaneous currents while switching. These currents, while high in magnitude, are very short in duration, typically lasting only a small fraction of the switching event. The very fast low-to-high and/or high-to-low demand for current during switching can be problematic for many digital circuit designs.
All current consumed by digital devices is provided by the circuit power supply. However, due to the physical properties of inductance and time transfer, the high instantaneous currents needed by digital devices during switching cannot come directly from the power supply. Instead, the conventional solution is to place capacitors near the digital devices. These capacitors act as local reservoirs of charge, which can be released quickly in the form of current when the demand requires it. A common name for capacitors used in this manner is xe2x80x9cdecoupling capacitorsxe2x80x9d.
However, these capacitors suffer from inductive properties as well. While their inductance is very much less than that of the power supply, the inductance is still problematic with very fast-switching digital circuits. The usual solution is to place many of these capacitors in a parallel grid structure across the power and ground connections of the digital devices. The overall inductive properties of capacitors combined in parallel tend to decrease while the capacitance itself increases.
Modern high-speed digital systems comprise one or more integrated circuit (IC) packages mounted on fiberglass boards called Printed Circuit Boards (PCBs). PCBs are formed of alternating laminated layers of fiberglass and metal, such as copper. Typically, each layer operates as either a power plane, a ground plane, or an interconnect layer providing routed metal lines between nodes in the circuit.
Prior art techniques mandate mounting decoupling capacitors on one of the outside PCB layers (i.e., the top or bottom layer) and connecting the positive and negative terminals of the capacitors to a respective power and ground plane within the PC board. The connections are made using vias. As known in the art, vias are formed by drilling holes in the PC and electroplating the walls of the hole with a conductor such as copper. A given layer in the PCB connects to a via if metal in that particular layer conductively connects to the conductive wall of the via. Accordingly, if no connection to the via is desired, the metal layer is etched around the location where the via will be formed to ensure that the layer does not make a conductive connection to the via. For example, a metal power layer will be etched around every negative via location, which connects to a ground plane, but will not be etched at positive via locations, which connect to power planes.
Large numbers of decoupling capacitors can be problematic. Their per-unit costs add up and can make products less cost-competitive in the marketplace. The physical space required for the capacitor grid on the PCB assemblies can make products larger, or displace ICs that can otherwise enhance a product""s features. Additionally, as more capacitors are needed to decouple digital ICs, they must be placed further and further away from the ICs that they are meant to decouple. The further the distance of a decoupling capacitor from the IC, the less its effect, leading to diminishing returns.
Reliability for a product diminishes as the number of decoupling capacitors increases. Intuitively, this is due to the fact that the more devices in a circuit, the more opportunity for and likelihood that a device will fail. Accordingly, increasing the effectiveness of decoupling capacitors would allow for fewer numbers and more reliability for the product.
Each instance of a decoupling capacitor includes at least one pair of vias that connect it to the power and ground planes buried within the printed circuit board. As previously described, vias are metal lined holes that selectively make contact to the conductive layers on and within the board. The vias themselves take up additional PCB space. Multiple via pairs per decoupling capacitor decreases the mounting inductance at the cost of more board space.
Accordingly, a need exists for a method of placing capacitors at higher density and without the induction problems associated with prior via sharing.
In accordance with the invention, a technique which allows decoupling capacitors to share vias without increasing detrimental inductive properties is presented. The novel shared-via interconnect technique allows a denser capacitor and via mounting pattern.
In accordance with the invention, vias are shared between capacitors mounted on the top and bottom of the PCB. This arrangements avoids the current doubling problem of prior art via-sharing methods when shared vias are connected with capacitors installed on the same side of the PCB board. In an illustrative embodiment, each decoupling capacitor is connected to the PCB by four vias. Accordingly, the total via count per capacitor is approximately two for large numbers of capacitors connected in accordance with the invention. By sharing vias between capacitors mounted on both sides of the PCB, the invention allows for the benefits of four vias per capacitor, while only approximately two vias per capacitor are actually implemented.
Additional vias per decoupling capacitor may be implemented to decrease the mounting inductance and resistance and therefore increase the effectiveness of the decoupling capacitor. Overall, because each decoupling capacitor is more effective than prior art decoupling capacitors, fewer decoupling capacitors are required for a given application.